EDSSI=Val_0x0, PTIME=Val_0x0, ELCOLR=Val_0x0, ETBEI=Val_0x0, ELSI=Val_0x0, ERBFI=Val_0x0
Interrupt Enable Register
| ERBFI | Enable Received Data Available Interrupt This bit is used to enable/disable the generation of Received Data Available interrupt and the Character Timeout interrupt (if FIFOs are enabled). These are the second highest priority interrupts. 0 (Val_0x0): Disable Received Data Available interrupt 1 (Val_0x1): Enable Received Data Available interrupt |
| ETBEI | Enable Transmit Holding Register Empty Interrupt This bit is used to enable/disable the generation of THRE Interrupt. This is the third highest priority interrupt. 0 (Val_0x0): Disable THRE interrupt 1 (Val_0x1): Enable THRE interrupt |
| ELSI | Enable Receiver Line Status Interrupt This bit is used to enable/disable the generation of Receiver Line Status interrupt. This is the highest priority interrupt. 0 (Val_0x0): Disable Receiver Line Status interrupt 1 (Val_0x1): Enable Receiver Line Status interrupt |
| EDSSI | Enable Modem Status Interrupt This bit is used to enable/disable the generation of Modem Status interrupt. This is the fourth highest priority interrupt. 0 (Val_0x0): Disable Modem Status interrupt 1 (Val_0x1): Enable Modem Status interrupt |
| ELCOLR | This bit controls the method for clearing the status in the UART_LSR register. This is applicable only for overrun error, parity error, framing error, and break interrupt status bits of UART_LSR register. 0 (Val_0x0): UART_LSR status bits are cleared either on reading Rx FIFO (UART_RBR) or on reading UART_LSR register. 1 (Val_0x1): UART_LSR status bits are cleared only on reading UART_LSR register. |
| PTIME | Programmable THRE Interrupt Mode Enable This bit is used to enable/disable the generation of THRE interrupt. 0 (Val_0x0): Disable programmable THRE interrupt mode 1 (Val_0x1): Enable programmable THRE interrupt mode |